1. Field of the Invention
The present invention relates to direct digital synthesizers, and more particularly relates to a direct digital synthesizer with a tracker circuit operating at high resolution and low power consumption which is able to accommodate both single frequency and chirped frequency operation.
2. Description of the Prior Art
Direct digital synthesizers (DDS) are well known in the prior art. FIG. 1 illustrates a conventional continuous wave (CW) direct digital synthesizer which numerically generates a sine wave output signal corresponding to a received numerical frequency value and phase clock signal. The DDS 2 consists primarily of three operating blocks; a phase accumulator circuit 4, a sine lookup circuit 6, and a digital to analog converter (DAC) 8. The phase accumulator circuit 4 includes a digital counter which receives the numerical frequency value signal and phase clock signal from an external controller. The phase accumulator circuit 4 increments the counter for each received clock signal by the value determined by the received frequency value signal.
The phase accumulator circuit 4 places the counter value on an output bus which is operatively coupled to the sine lookup circuit 6. The sine lookup circuit 6 is typically a read only memory (ROM) circuit which has a series of addressable locations. Each ROM location contains a value representing a phase value of the sine wave output signal. To generate the sine wave output signal, points along the full sine wave curve from 0 to 2.pi. must be generated. However, as the sine wave signal is symmetrical, this signal can be generated by storing values in the sine lookup circuit from 0 to .pi./2 (1/4 sine wave ROM). By incrementing, decrementing and inverting the values stored in the 1/4 sine wave ROM via the phase accumulator circuit 4, the full sine wave signal is generated using a sine lookup circuit 6 with a required capacity which is reduced by a factor of 4. The phase values from the sine lookup circuit 6 are operatively coupled to the DAC 8 which converts the digital phase values from the sine lookup circuit 6 to an analog sine wave output signal. The analog sine wave output signal is presented on an output terminal 8A of the DAC.
The phase accumulator circuit 4 may further include a phase preset input terminal 4A. When a value is received by the phase preset input terminal 4A, the phase accumulator circuit 4 presents a value to the sine lookup circuit 6 which corresponds to the received phase preset value. This feature is useful in phase modulation applications where a predetermined starting phase is important.
The frequency of the sine wave output signal generated by the DDS 2 is related to the frequency of the phase clock signal and the phase increment (resolution) determined by the received frequency value signal. The output frequency is equal to: ##EQU1## where N is the number of bits in the phase accumulator counter circuit and .increment..phi. is the phase increment applied to the phase accumulator.
The frequency resolution of the DDS 2 is determined by N, the number of bits in the phase accumulator counter circuit. At a predetermined minimum output frequency for a given received clock signal, the phase accumulator 4 will generate a signal with 2.sup.N different values. To generate higher frequency output signals, the phase accumulator circuit 4 eliminates a number of these output states at regular intervals from the counter output signal. This increases the phase step, .increment..phi., for each output of the phase accumulator counter circuit. Since a smaller number of points are used to define the sine wave and the clock rate is constant, the frequency of the output signal generated by the DDS 2 is increased. This is illustrated in the timing diagrams shown in FIGS. 1A and 1B.
It is also possible to generate a linear variable frequency output or chirp signal from a DDS. FIG. 2 illustrates the conventional topology for a chirp DDS 12. In order to perform the additional function of frequency chirping, a frequency accumulator 10 is added to the DDS of FIG. 1. The frequency accumulator 10 receives a start frequency value and a slope value from an external controller. The start frequency value sets the initial operating frequency of the chirp DDS 12 and the slope value determines the rate of change in frequency of the chirp DDS output signal. The frequency accumulator 10 generates a digital signal which is operatively coupled to a frequency value input terminal of the phase accumulator 4. This digital signal has a value which increases at a rate determined by the slope value. By driving the phase accumulator 4 with a variable frequency value, the values presented to the sine lookup circuit 6 will represent the desired variable output frequency.
In the DDS of FIGS. 1 or 2, it is desirable to achieve high output frequencies as well as high frequency resolution. The frequency resolution of the DDS is limited by the number of bits used in the accumulators (both phase and frequency). Further, the output frequency of the DDS is limited by the frequency of the received phase clock signal to the phase accumulator 4. Therefore, in order to generate a high frequency output signal from a DDS which also features fine resolution, high speed digital circuitry must be employed in the phase and frequency accumulator circuits. Typically, 32 bit architecture is employed within the accumulator circuits in order to achieve the desired frequency resolution. When circuitry of this complexity is operated at the required clock speeds to generate high frequency output signals, the DDS will consume a large amount of power. Typically, these high speed 32-bit circuits are also expensive and generate a significant amount of undesired heat, the removal of which results in further cost and system complexity.